ASIC Design Service


We provide full SoC implementation service with offering different entry points to the flow:

• Specification Signoff - Customer provides design specification. We perform all design flow to ASIC samples

• RTL Signoff - Customer provides synthesizable RTL code along with design constraint. We perform RTL to GDSII implementation and samples production

• Netlist Signoff - Customer provides verified gate level netlist. We make physical implementation and production

FPGA Design Service


Our FPGA Design Services include:

• ASIC Prototyping

Verification of ASIC/SoC design

• FPGA Emulation

Emulation of ASIC/SoC based design


• Design Convertion

FPGA to ASIC design convertion


• Pure FPGA design

Custom FPGA design

IP Service


List of avaliable in-house IP blocks includes:

• 64/32 bit RISC-V multi-core CPU

• Floating Point Unit (FPU)

• Direct Memory Access (DMA) Controller

• Low Speed AXI Periphery (UART, I2C, Timers, SPI, GPIO)


AMBA AXI Components